A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, for example, a photogate, photoconductor, or a photodiode for accumulating photo-generated charge in a portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output transistor, which receives photogenerated charges from a doped diffusion region (an electrically active area) and produces an output signal which is periodically read-out through a pixel access transistor. The imager may optionally include a transistor for transferring charge from the photoconversion device to the diffusion region or the diffusion region may be directly connected to or part of the photoconversion device. A transistor is also typically provided for resetting the diffusion region to a predetermined charge level before it receives the photoconverted charges.
A basic, three-transistor (3T) CMOS active pixel sensor (APS) design used in many applications contains a photodiode; a reset transistor, for resetting the photodiode voltage; a source follower transistor having a gate connected to the photodiode, for producing an output signal, and a row select transistor for selectively connecting the source follower to a column line of a pixel array. In a four-transistor (4T) configuration, a transfer transistor is employed to gate charges from the photodiode to the gate of the source follower transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
The transistors of CMOS imager circuits are typically n-channel MOSFETs. In other semiconductor technology, e.g., DRAM technology, n-channel transistors typically have LDD (lightly doped drain) implants to improve off-state leakage and punch through leakage for short gate length devices. However, when this technique is used for transistors associated with photodiodes of CMOS imager circuits such as, transfer or reset transistors, a problem is presented. The LDD implant on the photodiode side of the transistor causes high electric fields to the substrate, which results in higher imager dark current.
This problem associated with CMOS imagers is dark current generation. Pixel cells of CMOS imagers are typically electrically isolated from one another by STI (shallow trench isolation) regions, where trenches are etched into the substrate and filled with a dielectric. An LDD-type implant in the photodiode region of the pixel increases the electric field in that region, resulting in increased photodiode leakage or increased dark current. Another physical source of dark current produced by such an LDD implant would be along the transistor gate associated with the photodiode as well.
CCD imagers also include signal output circuitry, which includes at least an output transistor, a reset transistor, a floating diffusion region, a Vcc voltage source, a source follower transistor and a voltage output. This circuitry can also suffer from dark current generation and current leakage, which results in poor device performance.
A method and apparatus which mitigates the leakage and dark current problems, but which still enables effective punch-through protection would be advantageous.